Andy Wanna

I am a third-year Ph.D. student at Georgia Tech, advised by Prof. Callie Hao in the SHARC Lab. I build e-graph-based tools for hardware design automation. My Ph.D. is funded by AMD, where I am a Graduate Applied Researcher.

My research applies e-graphs (equivalence graphs) at each level of the hardware design stack. At the expression level, OptiMult optimizes multiplier architectures and was built with Intel and UCLA. At the HLS level, Lemonade finds reusable hardware modules across HLS programs, and ForgeBench generates the ML designs used to test HLS tools. At the netlist level, my work at AMD rewrites production standard-cell netlists of over 4 million cells. My current project, EGGROLL, uses reinforcement learning to guide e-graph exploration so these tools scale to larger designs.

Before Georgia Tech I completed an M.Eng. in Electronic and Information Engineering at Imperial College London (First Class, 2024). I have interned twice with AMD’s numerical hardware team (2025, 2026), with Intel’s numerical hardware team (2024), and with Quantum Motion, a silicon quantum computing startup in London.

I am looking for research internships for summer 2027 in EDA, logic synthesis, HLS and hardware compilers, and ML for chip design. My CV is here, and the best way to reach me is awanna3@gatech.edu.

Outside work: Formula 1, padel, and cooking.