CV

Ph.D. in Electrical and Computer Engineering (4.0 GPA)

Georgia Institute of Technology, Atlanta, Georgia, United States

• Expected graduation May 2028
• Advised by Prof. Callie Hao, SHARC Lab
• Ph.D. research funded by AMD as a Graduate Applied Researcher
• Coursework
  • SAT/SMT Solvers
  • Programming Languages
  • Hardware–Software Co-Design for ML Systems
  • FPGA Programming
  • Graphical Models in ML
  • High-Dimensional Statistics and Optimization
  • Advanced Programming Techniques
  • Internet Architecture and Protocols

M.Eng. in Electronic and Information Engineering, First Class Honours (4.0 GPA equivalent)

Imperial College London, London, United Kingdom

• First Class Honours in every year
• Dean's List in third year (top 10%) and fourth year (top 5%)
• M.Eng. thesis: OptINN, supervised by Prof. Wayne Luk and Dr. Ce Guo
• Relevant Modules
  • Advanced Computer Architecture
  • Advanced Deep Learning Systems
  • Digital System Design
  • Digital Arithmetic and Computer Architecture
  • Instruction Architectures and Compilers
  • Deep Learning
  • Mathematics for Machine Learning
  • Topics in Large Dimensional Data Processing
  • Probability and Stochastic Processes
  • Computer Vision
  • Digital Signal Processing
  • Operations Research
  • Embedded Systems

Numerical Hardware Engineer Intern

AMD, Numerical Hardware Team

• Built an e-graph rewriting tool over fully mapped standard-cell netlists, reducing cell count and area; measured figures under NDA
• Scaled the flow to production netlists of over 4 million cells, now under evaluation by AMD's IP synthesis team
• Extended the ILP extraction to stay tractable at netlist scale, with delay constrained, free, or optimized

Numerical Hardware Engineer Intern

AMD, Numerical Hardware Team, Folsom, California

• Designed integer and constant multiplier architectures that improve both minimum delay and area
• Designed an e-graph multiplier framework spanning array generation and reduction, enabling hybrid multiplier architectures
• Developed methods to generate multipliers optimized for input properties such as arrival times and toggle rates

Numerical Hardware Engineer Intern

Intel, Numerical Hardware Team (GPU group), London (remote)

• Automated mixed-precision floating-point multiplier optimization in Rust with e-graphs, improving PPA by up to 10%
• Investigated glitch power minimization in hardware designs using integer linear programming
• Explored methods for automatic dot-product hardware unit generation

FPGA Engineering Co-op

Quantum Motion, London

• Designed a bespoke FPGA signal generator for high-speed qubit feedback, integrated into the QICK stack in SystemVerilog with Vivado
• Extended QICK with a peak-tracking hardware control loop and improved signal-generator precision and range
• Built a Python library on PYNQ and QICK so lab users can drive the FPGA hardware
• Programmed an RP2040 microcontroller in C to communicate over TCP/IP on Ethernet using the lwIP library, porting lab functions to it

Analog and Digital IC Validation Intern

Quantum Motion, London

• Validated ring oscillators on silicon, analyzing transistor properties at room and cryogenic (2 K) temperatures
• Built a model predicting transistor threshold voltage from ring oscillator measurements
• Automated data analysis with Python scripting
• Designed a low-noise, wide-range (1 nA – 10 mA), wide-band (100 MHz) current sensor schematic and PCB

EGGROLL: Reinforcement Learning for E-Graph Exploration

Georgia Institute of Technology and AMD — first author, in preparation; invited demo, ARITH 2026

• Building a generalized RL framework to address the scalability limits of equality saturation
• Formulating equality saturation as a decision problem: e-graph as state, rewrite as action, sparse cost reward
• Matching or improving on expressions from exhaustive equality saturation with far smaller e-graphs
• Designed to apply to any e-graph framework given a language, rewrite set, analyses, cost function and extraction method; currently driving a netlist rewriting flow, guiding exploration away from e-graph blow-up on large designs

Lemonade: Automated HLS Design Modularization using E-Graphs

Georgia Institute of Technology — first author, under review

• Built an MLIR-based framework that automatically discovers reusable hardware modules across structurally distinct HLS programs, combining e-graphs, anti-unification, and polyhedral analysis
• Introduced polyhedral loop-mapping analysis deriving the minimal set of sound loop transformations that expose shared modules, pruning an 8,716M-candidate space to 4,096 designs (0.00005%)
• Designed decoupled hardware-oriented cost functions (a hardware impact cost for module extraction and a performance cost for implementation), reusing 38.1% of synthesized hardware across Polybench, GNN layers and transformer encoder blocks
• Composed with ScaleHLS for a geo-mean 47.8% lower area at iso-delay and 53.8% fewer cycles at iso-area
• Bit-exact equivalence verified in Vitis HLS C simulation; loop-rewrite legality checked with ISL
• Early version presented at the EGRAPHS workshop, PLDI 2025

ForgeBench: An HLS Design Generator of ML Test Suites for Next-Generation HLS Tools

Georgia Institute of Technology — co-first author, under review at ACM TRETS (FPT 2026 Journal Track); extends our FCCM 2026 poster

• Built a generator that composes synthesizable HLS C/C++ from a JSON specification over an extensible ML kernel library, so HLS tools can be developed against current ML workloads rather than legacy fixed benchmarks
• Generated full model-level designs for ResNet-18/34/50/101/152 and LLaMA-3.1-8B, including a complete 32-layer LLM project spanning prefill and decode, KV-cache, RoPE and attention, validated against a NumPy golden reference
• Demonstrated scale with a 12,912-design suite across GEMM, DNN and LLM workloads, with 2,711 designs placed and routed on a ZCU102, all meeting timing
• Built a modularization suite with hand-constructed shared-module baselines, plus a portable Catapult HLS backend and HLSFactory integration
• Tool-support study across ScaleHLS, HIDA, AutoSA, StreamHLS and Allo; on LLM designs every tool except Allo stops at parsing

SpecScore: Quantifying Readability of HLS-Generated RTL Using LLMs

Georgia Institute of Technology — co-first author, in preparation

• Proposed an automated, annotation-free RTL readability metric: the cosine similarity between an HLS C++ specification and its tool-generated RTL in a joint LLM embedding space
• Introduced four strategies for embedding RTL exceeding model context windows, including hierarchical module summarization, validated at 0.95 mean reciprocal rank on PolyBench, MachSuite and CHStone

Formal Verification of Hardware Arithmetic in Lean

Georgia Institute of Technology

• Built a Rust-to-Lean 4 flow verifying RTL arithmetic datapaths against a bitvector DSL specification, translating Verilog via Yosys and AIGER and discharging equivalence with bv_decide and CaDiCaL
• Designed a type-explicit arithmetic DSL forcing a bitwidth on every wire, 3.64× more concise than equivalent RTL
• Implemented canonical bitwidth reconciliation, mapping hardware's n, m → k operators onto Lean's BitVec

OptiMult: Multiplier Optimization via E-Graph Rewriting

Imperial College London, with Intel and UCLA — first author, ASILOMAR 2023

• Built an e-graph rewriting tool in Rust on egg that explores equivalent multiplier architectures as local equivalence-preserving rewrites and emits synthesizable Verilog
• Introduced a dual row and column representation of AND arrays, and a two-phase optimization with separate rewrite sets and delay cost models per phase to keep gate-level search tractable
• Cut latency by up to 46% on squarers and 9% on multipliers against a commercial synthesis tool at TSMC 5nm, with every design formally verified by equivalence checking

OptINN: Breaking the Interpretability–Efficiency Trade-off for DNNs on GPUs

Imperial College London — M.Eng. thesis

• Designed a prototype-based interpretable architecture that recasts prototype distance as GPU-optimized convolutions with hard-sigmoid activations, for full cuDNN and TensorRT support
• Built a toolchain compiling pretrained CNNs into optimized interpretable TensorRT engines, with principled quantize/dequantize node placement and quantization-aware training for INT8
• Showed prototype interpretability resists quantization: I-Score moves under 0.03 from FP32 to INT8 while latency falls up to 84.4%, and MobileNet-V3 runs interpretably in 2.10 ms against 8.35 ms for the original CNN

ForgeBench: An HLS Design Generator of Machine Learning Test Suites for Next-Generation HLS Tools

Co-first author. Under review at ACM TRETS (FPT 2026 Journal Track). Extends our FCCM 2026 poster.

CRYPTONITE: Scalable Accelerator Design for Cryptographic Primitives and Algorithms

Third author. IEEE ASAP 2025.

Multiplier Optimization via E-Graph Rewriting

First author. Asilomar Conference on Signals, Systems, and Computers 2023.

Invited demo — EGGROLL

ARITH 2026

Poster — ForgeBench

FCCM 2026, Atlanta

Talk — Lemonade (early version)

EGRAPHS workshop, PLDI 2025

AMD Graduate Applied Researcher

Ph.D. research funded by an AMD gift and a sponsored research agreement

ACM/IEEE DAC Young Student Fellow

Dean's List, Imperial College London

Top 10% of cohort in third year, top 5% in fourth

Graduate Teaching Assistant, CS 4240 Compilers

Georgia Tech. Delivered a lecture on the MIPS ISA and ran the lab autograder.

Reviewer, IEEE Transactions on Computers

Mentor to an M.Sc. student

Work published at ASAP 2025

Teaching Assistant, ELEC40013 Mathematics

Imperial College London

Vice-President, Electrical Engineering Society

Imperial College London

Year 2 Academic Representative

Imperial College London

Deep Learning Activation Function Hardware Accelerators in SystemVerilog

• Designed and verified 4–16-bit parameterized implementations of Softmax, LogSigmoid, Sigmoid, ELU, SiLU and Softshrink
• Integrated the activation functions into a reconfigurable, dynamically scheduled hardware architecture

Cosine Accelerator on FPGA

• Reduced the output latency of a vector function by 77% with a custom CORDIC cosine block in SystemVerilog (Quartus)
• Designed custom floating-point arithmetic blocks and optimized further with low-level C

Digital Synthesizer in Embedded C

• Programmed an STM32 microcontroller with multi-threading in embedded C, adding features while keeping thread safety and sound-output latency
• Enabled automatic detection and integration of additional devices

Energy Efficiency of a Superscalar CPU

• Varied microarchitectural parameters (branch predictors, memory hierarchy, instruction parallelism) and measured their impact on energy

C to MIPS Assembly Compiler in C++

• Object-oriented compiler handling pointer arithmetic, arrays and function calls

MIPS 32-bit CPU in Verilog

• 32-bit MIPS CPU in Verilog with test benches covering edge cases for each instruction

Generative and Computer Vision Models in PyTorch

• U-Net segmentation of brain MRI scans; VAE on MNIST; class-conditional and Wasserstein-GP DCGANs on CIFAR-10

Web and Embedded Systems Projects

• Mars Rover web app (Node.js, Express, MySQL on AWS); GymBro Raspberry Pi device with multi-user backend and authentication; FPGA hand-held game controller with a NIOS-II soft core