CV

Ph.D of Computer Engineering

Georgia Institute of Technology, Georgia, United States

• Year 1
  • 4.0 GPA
• Year 2
  • 4.0 GPA
• Relevant Modules
  • SAT/SMT Solvers (SW)
  • Internet Architecture and Protocols (SW/HW)
  • Hardware-Software Co-Design in ML systems (HW/DL)
  • Graphical Models in ML (DL)
  • High Dimensional Statistics and Optimization (DL)
  • Advanced Programming Techniques (HW/SW)

Masters of Engineering (Computer Engineering) - First Class Honors (4.0 GPA)

Imperial College London, London, United Kingdom

• Year 1
  • First Class Honors (4.0)
• Year 2
  • First Class Honors (4.0)
• Year 3
  • First Class Honors (4.0)
  • Dean's List (Top 10% of Year)
• Year 4
  • First Class Honors (4.0)
  • Dean's List (Top 5% of Year)
• Relevant Modules
  • Advanced Computer Architecture (HW)
  • Advanced Deep Learning Systems (HW/DL)
  • Digital System Design (HW)
  • Deep Learning (DL)
  • Topics in Large Dimensional Data Processing (DL)
  • Mathematics for Machine Learning (DL)
  • Financial Signal Processing and Machine Learning (DL)
  • Probability and Stochastic Processes (DSP/DL)
  • Computer Vision (DL)
  • Introduction to Machine Learning (DL)
  • Digital Signal Processing (DSP)
  • Instruction Architectures & Compilers (HW)
  • Information Processing (HW)
  • Digital Arithmetic and Computer Architecture (HW)
  • Operations Research (SW)
  • Embedded Systems (SW)
  • Software Systems (SW)
  • Discrete Maths (SW)
  • Programming (SW)

International Baccalaureate

Dhahran High School, Dhahran, Saudi Arabia

• IB
• SAT + SAT Subject tests

Numerical Hardware Engineer Intern

AMD, Folsom, California, United Stated of America

• Invented novel integer and constant multiplier architectures, improving both minimum delay and area
• Designed E-Graph multiplier framework capturing array creation and reduction design space, enabling exploration of arbitrarily hybrid architectures
• Developed methods to automatically generate multipliers optimized to input data properties such as arrival time and toggle rates

Numerical Hardware Engineer Intern

Intel, London (Remote), United Kingdom

• Automated mixed-precision floating point multiplier design optimization in Rust using E-Graph
• Investigated glitch power minimization in hardware designs using Integer Linear Programming
• Explored techniques and methods for optimal dot-product hardware units

FPGA Engineer Co-Op

Quantum Motion Technologies, London, United Kingdom

• Designed and integrated bespoke signal generator into QICK stack for High-Speed Qubit Feedback on an FPGA in System Verilog, using Vivado
• Built a high-level, user-friendly software library to interface with and take advantage of optimised FPGA hardware with PYNQ and QICK Python libraries
• Programmed an RP2040 to communicate using TCP/IP over ethernet connections in C using the light-weight IP library
• Ported functions into C to be used on the RP2040, building an extensive codebase

Analogue and Digital IC Validation Intern

Quantum Motion

• Automated Data analysis using Python scripting
• Devised model predicting transistor threshold voltage based on ring oscillator measurements
• Validated operation of ring oscillator hardware on silicon chips
• Characterized properties of silicon across a range of chips, at room and cryogenic Temperatures (2K)
• Designed low-noise, wide range (1na-10ma), wide-band (100MHz) current sensor schematic and PCB

E-Graph Reinforcement Learning Framework

Georgia Institute of Technology - AMD - Current Research

• Building a generalized RL framework to streamline e-graph exploration, addressing scalability limitations

Hardware Arithmetic Formal Verification in Lean

Georgia Institute of Technology - Current Research

• Framework built in Lean to formally verify arithmetic RL designs against a strict bitvector arithmetic DSL
• Developed a Yosys-based frontend for Verilog designs alongside the DSL parser, in Rust
• Support for SMT-based proofs, parameterized model checks, multiplier verification, and floating point properties

Lemonade: Automated HLS Design Modularization using E-Graphs - Primary Co-Author

Georgia Institute of Technology

• Developed a framework integrating e-graphs, anti-unification, and polyhedral loop analysis to automatically identify and extract reusable hardware modules from HLS designs
• Introduced hardware-aware cost functions to guide module selection and design extraction, enabling scalable reuse across diverse workloads including GEMM, GEMV, and self-attention
• Demonstrated up to 99% hardware reuse and significant area reductions across benchmarks, with modularized designs synthesized on FPGA/ASIC flows (Catapult HLS, Vitis HLS)
• Presented at PLDI 2025
• Under Review

ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework - Primary Co-Author

Georgia Institute of Technology

• An extensible benchmark framework auto-generating HLS ML designs across GEMM, DNN, and LLM workloads
• Created a modularized benchmark test suite demonstrating the necessity of architecture-oriented HLS tools

Quantifying and Automating Interpretability for Deep Learning - Final Year Project - Primary Author

Imperial College London

• Designed metric to quantitatively evaluate the interpretability of a deep learning model, enabling trade-off analysis
• Developed an automated workflow to add interpretability to CNNs, achieving up to an 84\% inference latency improvement over the manual INN model
• Demonstrated comparable interpretability results on standard CNNs with state-of-the-art GradCAM methods

OptiMult: Multiplier Optimization via E-Graph Rewriting - Undergraduate Research - Primary Author

Imperial College London - Under

• Created tool in Rust to compile hardware arithmetic expressions into optimized representations for area and latency
• Demonstrated up to a 46% latency reduction in squarer circuits and 9% latency reduction in general multiplication against industry standard logic synthesis tools
• Presented at ASILOMAR 2023

Deep Learning Activation Function Hardware Accelerators in SystemVerilog

• Designed and Verified 4 – 16 bit parameterized implementations of Softmax, LogSigmoid, Sigmoid, ELU, SILU, Softshrink activation functions
• Integrated activation functions into a re-configurable, dynamically scheduled hardware architecture

Generative Deep Learning Models in PyTorch

• Analyzed a VAE transformer architecture on generating and classifying the MNIST dataset
• Explored Class Conditional & Wasserstein-GP DCGAN architectures on generating images in the CIFAR-10 dataset

Cosine Accelerator on FPGA in Verilog

• Reduced the output latency of vector function by 77% by implementing custom cosine block on an FPGA using CORDIC in SystemVerilog with Quartus
• Designed customized hardware Floating-Point Arithmetic blocks for further speed-ups
• Optimized function further via low-level programming in C

MRI Diagnosis Model using Computer Vision in PyTorch

• Implemented U-Net CNN architecture to perform image classification and segmentation on brain scans

Digital Synthesizer in Embedded C

• Programmed an STM32 micro-controller using Multi-Threading in Embedded C
• Developed advanced functionality while maintaining thread safety, without affecting latency of sound output
• Enabled automatic detection and integration of additional devices to expand the synthesizer's functionality

GymBro Embedded Raspberry PI Device

• Built a network hosting an AWS server, a Raspberry Pi Client, and MySQL Database
• Expanded functionality for multiple concurrent users, using Express.js, Node.js and MySQL
• Ensured security by adding user authentication

Maximized Energy Efficiency of a SuperScalar CPU by varying MicroArchitectural Parameters

• Varied microarchitectural parameters such as Branch Predictors, Memory Hierarchy, and Instruction Parallelism, investigating their impact on energy usage

House Price Regression Model in PyTorch

• Designed a regression model using a neural network
• Preformed data pre-processing, K-fold hyperparameter validation, early stopping, batched gradient descent and various other ML optimization techniques
• Implemented a custom NN training and inference mini library with batched gradient descent, arbitrary layers and custom activation functions

Webapp for Mars Rover

• Developed backend for webserver using AWS, Node.js and Express.js for communication between the webapp and embedded system on Mars Rover
• Designed front-end with HTML/CSS/JavaScript
• Utilized MySQL on an AWS instance as a database for the WebApp, to maintain live rover position and data

C to MIPS Assembly compiler in C++

• Object-Oriented compiler
• Compiles complex expressions in C such as pointer arithmetic, arrays and advanced function calls

Automatic Scheduler in C++

• Created software to allocate projects within a set schedule to improve time management in C++

Video game with FPGA hand-held controller

• Instantiated NIOS-II soft-core CPU onto FPGA using Quartus
• Programmed FPGA accelerometer functionality and low-level local processing and networking in C with Eclipse
• Developed client-side communication with server and user along with advanced signal processing for motion detection in Python

MIPS 32-bit CPU in Verilog

• MIPS 32-bit CPU written in Icarus Verilog to process standard instructions
• Wrote test-benches to systematically test edge cases for each instruction

Boolean Algebra Solver in C++

• Programmed tool that could reduce and solve Boolean algebra expressions using trees in C++

Vice-President of Electrical Engineering Society

Year 2 Academic Representative

Fundraising Officer at Habitat for Humanity

President of Robotics Club

Founder of BISAK Tutoring Club